US Patent Application 18362198. Novel Bank Design with Differential Bulk Bias in eFuse array simplified abstract

Novel Bank Design with Differential Bulk Bias in eFuse array

Organization Name

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor(s)

Meng-Sheng Chang of Chubei City (TW)

Chia-En Huang of Xinfeng Township (TW)

Novel Bank Design with Differential Bulk Bias in eFuse array - A simplified explanation of the abstract

This abstract first appeared for US patent application 18362198 titled 'Novel Bank Design with Differential Bulk Bias in eFuse array

Simplified Explanation

The abstract describes a memory circuit that includes multiple memory cells and transistors.

• The memory circuit includes a first memory cell with a resistor and a first transistor.
• The first transistor has a bulk port biased at a first voltage level.
• There is a second memory cell connected to the first memory cell, which also has a resistor.
• The second memory cell is coupled to a second transistor with a bulk port biased at a second voltage level.
• The second voltage level is lower than the first voltage level.

Original Abstract Submitted

In some aspects of the present disclosure, a memory circuit is disclosed. In some aspects, the memory circuit includes a first memory cell including a first resistor; and a first transistor coupled to the first resistor, wherein a first bulk port of the first transistor is biased at a first voltage level; a second memory cell coupled to the first memory cell, the second memory cell including a second resistor; and a second transistor coupled to the second memory cell, wherein a second bulk port of the second transistor is biased at a second voltage level, wherein the second voltage level is less than the first voltage level.