US Patent Application 18361722. INTEGRATED CIRCUIT IN HYBRID ROW HEIGHT STRUCTURE simplified abstract

INTEGRATED CIRCUIT IN HYBRID ROW HEIGHT STRUCTURE

Organization Name

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor(s)

Jerry Chang-Jui Kao of Taipei City (TW)

Hui-Zhong Zhuang of Kaohsiung City (TW)

Li-Chung Hsu of Hsinchu City (TW)

Sung-Yen Yeh of Pingtung County (TW)

Yung-Chen Chien of Kaohsiung City (TW)

Jung-Chan Yang of Taoyuan City (TW)

Tzu-Ying Lin of Hsinchu City (TW)

INTEGRATED CIRCUIT IN HYBRID ROW HEIGHT STRUCTURE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18361722 titled 'INTEGRATED CIRCUIT IN HYBRID ROW HEIGHT STRUCTURE

Simplified Explanation

The abstract describes an integrated circuit that includes two circuits - a first circuit with multiple transistors and a second circuit with a single transistor.

• The first circuit is arranged in a row of cells with a certain number of fin structures.
• The second transistor is connected in parallel with one of the transistors in the first circuit.
• The second transistor is arranged in a different row of cells with a different number of fin structures.
• The first transistor and the second transistor share a common gate that extends through both rows of cells.
• The second transistor is essentially a duplicate of the first transistor.

Innovation:

• The integrated circuit allows for the parallel connection of transistors from different circuits.
• The use of different cell rows with varying numbers of fin structures allows for optimization of the circuit layout.
• The shared gate between the first and second transistors simplifies the circuit design and reduces the overall size of the integrated circuit.

Original Abstract Submitted

An integrated circuit is provided and includes first transistors of a first circuit arranged in a first cell row having a first number of fin structures and a second transistor of a second circuit. The second transistor is coupled in parallel with a first element in the first transistors between first and second terminals of the first circuit, and arranged in a second cell row having a second number, different from the first number, of fin structures. The first element and the second transistor share a first gate extending in a first direction to pass through the first and second cell rows in a layout view. The second transistor is a duplication of the first element.