US Patent Application 18361717. INNER FILLER LAYER FOR MULTI-PATTERNED METAL GATE FOR NANOSTRUCTURE TRANSISTOR simplified abstract
INNER FILLER LAYER FOR MULTI-PATTERNED METAL GATE FOR NANOSTRUCTURE TRANSISTOR
Organization Name
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s)
Shahaji B. More of Hsinchu (TW)
Chandrashekhar Prakash Savant of Hsinchu (TW)
INNER FILLER LAYER FOR MULTI-PATTERNED METAL GATE FOR NANOSTRUCTURE TRANSISTOR - A simplified explanation of the abstract
This abstract first appeared for US patent application 18361717 titled 'INNER FILLER LAYER FOR MULTI-PATTERNED METAL GATE FOR NANOSTRUCTURE TRANSISTOR
Simplified Explanation
The patent application describes an integrated circuit that includes two nanostructure transistors.
- The integrated circuit is formed by depositing an inter-sheet fill layer between the semiconductor nanostructures of the second nanostructure transistor.
- A first gate metal layer is then deposited between the semiconductor nanostructures of the first nanostructure transistor, while the inter-sheet filler layer is present between the semiconductor nanostructures of the second nanostructure transistor.
- The purpose of the inter-sheet filler layer is to prevent the deposition of the first gate metal between the semiconductor nanostructures of the second nanostructure transistor.
Original Abstract Submitted
An integrated circuit includes a first nanostructure transistor and a second nanostructure transistor. When forming the integrated circuit, an inter-sheet fill layer is deposited between semiconductor nanostructures of the second nanostructure transistor. A first gate metal layer is deposited between semiconductor nanostructures of the first nanostructure transistor while the inter-sheet filler layer is between the semiconductor nanostructures of the second nanostructure transistor. The inter-sheet filler layer is utilized to ensure that the first gate metal is not deposited between the semiconductor nanostructures of the second nanostructure transistor.
