US Patent Application 18361480. CHIP PACKAGE STRUCTURE WITH CONDUCTIVE PILLAR simplified abstract

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CHIP PACKAGE STRUCTURE WITH CONDUCTIVE PILLAR

Organization Name

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor(s)

Heh-Chang Huang of Hsinchu City (TW)

Fu-Jen Li of Hsinchu City (TW)

Pei-Haw Tsao of Tai-chung (TW)

Shyue-Ter Leu of Hsinchu City (TW)

CHIP PACKAGE STRUCTURE WITH CONDUCTIVE PILLAR - A simplified explanation of the abstract

This abstract first appeared for US patent application 18361480 titled 'CHIP PACKAGE STRUCTURE WITH CONDUCTIVE PILLAR

Simplified Explanation

The abstract describes a chip package structure that includes multiple components and layers.

  • The chip package structure includes a first chip structure with a substrate and an interconnect layer.
  • A second chip structure is placed over the interconnect layer.
  • A first conductive bump connects the interconnect layer to the second chip structure.
  • A conductive pillar is positioned over the interconnect layer, with its thickness equal to the combined thickness of the second chip structure and the first conductive bump.
  • A molding layer surrounds the second chip structure, the first conductive bump, and the conductive pillar.
  • A second conductive bump is located on the first surface of the conductive pillar.


Original Abstract Submitted

A chip package structure is provided. The chip package structure includes a first chip structure including a substrate and an interconnect layer over the substrate. The chip package structure includes a second chip structure over the interconnect layer. The chip package structure includes a first conductive bump connected between the interconnect layer and the second chip structure. The chip package structure includes a conductive pillar over the interconnect layer, wherein a first thickness of the conductive pillar is substantially equal to a sum of a second thickness of the second chip structure and a third thickness of the first conductive bump. The chip package structure includes a molding layer over the interconnect layer and surrounding the second chip structure, the first conductive bump, and the conductive pillar. The chip package structure includes a second conductive bump over a first surface of the conductive pillar.

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