US Patent Application 18361429. SCALABLE PATTERNING THROUGH LAYER EXPANSION PROCESS AND RESULTING STRUCTURES simplified abstract
Contents
SCALABLE PATTERNING THROUGH LAYER EXPANSION PROCESS AND RESULTING STRUCTURES
Organization Name
Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s)
Sai-Hooi Yeong of Zhubei City (TW)
SCALABLE PATTERNING THROUGH LAYER EXPANSION PROCESS AND RESULTING STRUCTURES - A simplified explanation of the abstract
This abstract first appeared for US patent application 18361429 titled 'SCALABLE PATTERNING THROUGH LAYER EXPANSION PROCESS AND RESULTING STRUCTURES
Simplified Explanation
The patent application describes a method for creating small and closely spaced features by patterning a layer with holes and then expanding the layer to shrink the holes. This process allows for the formation of multiple smaller holes from one larger hole, achieving smaller and closer spaced features than previously possible.
- Method for creating small and closely spaced features
- Patterning a layer with holes
- Expanding the layer to shrink the holes
- Formation of multiple smaller holes from one larger hole
- Achieving smaller and closer spaced features than previously possible
- Process includes implanting a dopant species with larger atomic spacing
Original Abstract Submitted
Small sized and closely pitched features can be formed by patterning a layer to have holes therein and then expanding the layer so that the holes shrink. If the expansion is sufficient to pinch off the respective holes, multiple holes can be formed from one larger hole. Holes smaller and of closer pitch than practical or possible may be obtained in this way. One process for expanding the layer includes implanting a dopant species having a larger average atomic spacing than does the material of the layer.
