US Patent Application 18361122. Methods for Fabricating FinFETs Having Different Fin Numbers and Corresponding FinFETs Thereof simplified abstract

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Methods for Fabricating FinFETs Having Different Fin Numbers and Corresponding FinFETs Thereof

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Jhon Jhy Liaw of Hsinchu County (TW)

Methods for Fabricating FinFETs Having Different Fin Numbers and Corresponding FinFETs Thereof - A simplified explanation of the abstract

This abstract first appeared for US patent application 18361122 titled 'Methods for Fabricating FinFETs Having Different Fin Numbers and Corresponding FinFETs Thereof

Simplified Explanation

The patent application describes a method for patterning fins in integrated circuits (ICs) that allows for different numbers of fins in different regions of the ICs.

  • The method uses a spacer lithography technique to form a fin pattern in a substrate.
  • The fin pattern includes a first fin line and a second fin line.
  • The spacing between the first and second fin lines is different in different regions of the IC.
  • In a first region corresponding to a single-fin FinFET, the spacing is greater.
  • In a second region corresponding to a multi-fin FinFET, the spacing is smaller.
  • This difference in spacing helps to relax process margins during a fin cut last process.
  • The fin cut last process involves partially removing a portion of the second fin line in the second region to form a dummy fin tip.
  • The spacing between the dummy fin tip and the first fin in the second region is greater than the spacing between the first and second fin lines.


Original Abstract Submitted

Fin patterning methods disclosed herein achieve advantages of fin cut first techniques and fin cut last techniques while providing different numbers of fins in different IC regions. An exemplary method implements a spacer lithography technique that forms a fin pattern that includes a first fin line and a second fin line in a substrate. The first fin line and the second fin line have a first spacing in a first region corresponding with a single-fin FinFET and a second spacing in a second region corresponding with a multi-fin FinFET. The first spacing is greater than the second spacing, relaxing process margins during a fin cut last process, which partially removes a portion of the second line in the second region to form a dummy fin tip in the second region. Spacing between the dummy fin tip and the first fin in the second region is greater than the second spacing.

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