US Patent Application 18360080. Semiconductor Gate-All-Around Device simplified abstract
Contents
Semiconductor Gate-All-Around Device
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.==Inventor(s)==
[[Category:Jhon Jhy Liaw of Hsinchu County (TW)]]
Semiconductor Gate-All-Around Device - A simplified explanation of the abstract
This abstract first appeared for US patent application 18360080 titled 'Semiconductor Gate-All-Around Device
Simplified Explanation
- The patent application describes a metal-oxide semiconductor field effect transistor (MOSFET) design. - The MOSFET includes a substrate and a well with dopants of a first conductivity-type. - An anti-punch-through (APT) layer is present in the upper section of the well, containing the same dopants as well as carbon. - The MOSFET also includes a source feature and a drain feature adjacent to the APT layer, with a second conductivity-type opposite to the first. - Multiple channel layers are stacked vertically over the APT layer, connecting the source and drain features. - The MOSFET features a gate that wraps around each of the channel layers, similar to a gate-all-around device. - The gate is positioned between the bottommost channel layer and the APT layer.
Original Abstract Submitted
A metal-oxide semiconductor field effect transistor (MOSFET) includes a substrate and a well over the substrate, the well including dopants of a first conductivity-type. The well includes an anti-punch-through (APT) layer at an upper section of the well, the APT layer including the dopants of the first conductivity-type and further including carbon. The MOSFET further includes a source feature and a drain feature adjacent the APT layer, being of a second conductivity-type opposite to the first conductivity-type. The MOSFET further includes multiple channel layers over the APT layer and connecting the source feature to the drain feature, wherein the multiple channel layers are vertically stacked one over another. The MOSFET further includes a gate wrapping around each of the channel layers, such as in a gate-all-around device, wherein a first portion of the gate is disposed between a bottommost one of the channel layers and the APT layer.
