US Patent Application 18360007. FIN END ISOLATION STRUCTURE FOR SEMICONDUCTOR DEVICES simplified abstract

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FIN END ISOLATION STRUCTURE FOR SEMICONDUCTOR DEVICES

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

JHON JHY Liaw of Hsinchu County (TW)

FIN END ISOLATION STRUCTURE FOR SEMICONDUCTOR DEVICES - A simplified explanation of the abstract

This abstract first appeared for US patent application 18360007 titled 'FIN END ISOLATION STRUCTURE FOR SEMICONDUCTOR DEVICES

Simplified Explanation

The patent application describes a method for forming a fin protruding from a substrate and creating gate structures across the fin.

  • The first gate structure faces the second gate structure, and a segment of the fin between the gate sidewalls is recessed to form a trench.
  • A dielectric layer is then deposited over the gate sidewalls and within the trench.
  • An inter-layer dielectric layer is also deposited over the gate structures and the dielectric layer.
  • A portion of the inter-layer dielectric layer is located within the trench.


Original Abstract Submitted

A method includes forming a fin protruding from a substrate, forming first and second gate structures across the fin, the first gate structure having a first gate sidewall facing the second gate structure, the second gate structure having a second gate sidewall facing the first gate structure, recessing a segment of the fin between the first and second gate sidewalls to form a trench, depositing a dielectric layer over the first and second gate sidewalls and within the trench, and depositing an inter-layer dielectric layer over the first and second gate structures and over the dielectric layer. A portion of the inter-layer dielectric layer is within the trench.

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