US Patent Application 18359070. Low-Resistance Interconnect simplified abstract

Low-Resistance Interconnect

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Hsin-Yen Huang of New Taipei City (TW)

Shao-Kuan Lee of Hsinchu (TW)

Cheng-Chin Lee of Hsinchu (TW)

Hsiang-Wei Liu of Tainan City (TW)

Tai-I Yang of Hsinchu City (TW)

Chia-Tien Wu of Taichung City (TW)

Hai-Ching Chen of Hsinchu City (TW)

Shau-Lin Shue of Hsinchu (TW)

Low-Resistance Interconnect - A simplified explanation of the abstract

This abstract first appeared for US patent application 18359070 titled 'Low-Resistance Interconnect

Simplified Explanation

- The patent application describes a method for forming integrated circuit devices. - The method involves starting with a workpiece that includes a first metal feature in a dielectric layer and a capping layer over the first metal feature. - A blocking layer is selectively deposited over the capping layer to prevent the deposition of an etch stop layer (ESL) over the capping layer. - The ESL is then deposited over the workpiece. - The blocking layer is removed. - Finally, a second metal feature is deposited over the workpiece, electrically coupling the first metal feature to the second metal feature.

Original Abstract Submitted

Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a first metal feature in a dielectric layer and a capping layer over the first metal feature, selectively depositing a blocking layer over the capping layer, depositing an etch stop layer (ESL) over the workpiece, removing the blocking layer, and depositing a second metal feature over the workpiece such that the first metal feature is electrically coupled to the second metal feature. The blocking layer prevents the ESL from being deposited over the capping layer.