US Patent Application 18358202. MEMORY ARRAY TEST METHOD AND SYSTEM simplified abstract

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MEMORY ARRAY TEST METHOD AND SYSTEM

Organization Name

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor(s)

Chien-Hao Huang of Hsinchu (TW)

Katherine H. Chiang of Hsinchu (TW)

Cheng-Yi Wu of Hsinchu (TW)

Chung-Te Lin of Hsinchu (TW)

MEMORY ARRAY TEST METHOD AND SYSTEM - A simplified explanation of the abstract

This abstract first appeared for US patent application 18358202 titled 'MEMORY ARRAY TEST METHOD AND SYSTEM

Simplified Explanation

The patent application describes a method for testing a non-volatile memory (NVM) array. Here are the key points:

  • The NVM array is heated to a target temperature.
  • A subset of the NVM cells are programmed to first resistance levels and the resulting current distribution is obtained.
  • The subset of NVM cells are then programmed to second resistance levels and the resulting current distribution is obtained.
  • A current threshold level is calculated based on the first and second current distributions.
  • Each NVM cell is programmed to either the first or second resistance level.
  • The current threshold level is used to determine a pass/fail status for each NVM cell at the programmed resistance level.
  • The bit error rate (BER) of the NVM array is calculated based on the first and second current distributions and the pass/fail status of each NVM cell.


Original Abstract Submitted

A method of testing a non-volatile memory (NVM) array includes heating the NVM array to a target temperature, and while the NVM array is heated to the target temperature, programming a subset of the NVM cells to first resistance levels and obtaining a first current distribution, programming the subset of NVM cells to second resistance levels and obtaining a second current distribution, calculating a current threshold level from the first and second current distributions, and for each of the NVM cells, programing the NVM cell to one of the first or second resistance levels, and using the current threshold level to determine a first pass/fail (P/F) status and a second P/F status at the programmed resistance level. A bit error rate (BER) of the NVM array is calculated based on the first and second current distributions and the first and second P/F status of each of the NVM cells.

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