US Patent Application 18357769. SERIES OF PARALLEL SENSING OPERATIONS FOR MULTI-LEVEL CELLS simplified abstract
Contents
SERIES OF PARALLEL SENSING OPERATIONS FOR MULTI-LEVEL CELLS
Organization Name
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s)
Mahmut Sinangil of Campbell CA (US)
Yen-Ting Lin of San Jose CA (US)
Kerem Akarvardar of Hsinchu (TW)
Carlos H. Diaz of Los Altos Hills CA (US)
SERIES OF PARALLEL SENSING OPERATIONS FOR MULTI-LEVEL CELLS - A simplified explanation of the abstract
This abstract first appeared for US patent application 18357769 titled 'SERIES OF PARALLEL SENSING OPERATIONS FOR MULTI-LEVEL CELLS
Simplified Explanation
The patent application describes a circuit and method for reading or sensing multiple bits of data stored in a multi-level cell.
- The circuit selects a first reference circuit from a set of reference circuits and a second reference circuit from another set of reference circuits.
- These reference circuits are used to determine one or more bits of the data stored in the multi-level cell.
- Based on the determined bits, the circuit selects a third reference circuit from the first set and a fourth reference circuit from the second set.
- These additional reference circuits are used to determine more bits of the data stored in the multi-level cell.
Original Abstract Submitted
Disclosed herein are related to a circuit and a method of reading or sensing multiple bits of data stored by a multi-level cell. In one aspect, a first reference circuit is selected from a first set of reference circuits, and a second reference circuit is selected from a second set of reference circuits. Based at least in part on the first reference circuit and the second reference circuit, one or more bits of multiple bits of data stored by a multi-level cell can be determined. According to the determined one or more bits, a third reference circuit from the first set of reference circuits and a fourth reference circuit from the second set of reference circuits can be selected. Based at least in part on the third reference circuit and the fourth reference circuit, additional one or more bits of the multiple bits of data stored by the multi-level cell can be determined.
