US Patent Application 18356350. SEMICONDUCTOR PACKAGE simplified abstract

SEMICONDUCTOR PACKAGE

Organization Name

Samsung Electronics Co., Ltd.

Inventor(s)

Sangcheon Park of Hwaseong-si (KR)

Youngmin Lee of Suwon-si (KR)

SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18356350 titled 'SEMICONDUCTOR PACKAGE

Simplified Explanation

The patent application describes a semiconductor package design that includes multiple semiconductor chips and various layers for connectivity and protection.

• The package includes a first semiconductor chip with front surface pads on one side and a penetrating electrode connected to these pads.
• A rear surface cover layer is placed on the inactive side of the first semiconductor chip for protection.
• A dummy conductive layer is included on the rear surface cover layer, which penetrates a portion of it.
• A second semiconductor chip is also part of the package, with a front surface cover layer on its active side.
• This second chip also has a dummy conductive layer that penetrates a portion of its front surface cover layer.
• The package includes at least one bonded pad that penetrates both the rear surface cover layer of the first chip and the front surface cover layer of the second chip.
• The purpose of this design is to provide improved connectivity and protection for the semiconductor chips within the package.

Original Abstract Submitted

A semiconductor package includes: a first semiconductor chip including a plurality of front surface pads disposed on a first active surface of a first semiconductor substrate, at least one penetrating electrode penetrating at least a portion of the first semiconductor substrate and connected to the front surface pads, a first rear surface cover layer disposed on a first inactive surface of the first semiconductor substrate, a first rear surface dummy conductive layer penetrating a portion of the first rear surface cover layer; a second semiconductor chip including a second front surface cover layer disposed on a second active surface of a second semiconductor substrate, and a second front surface dummy conductive layer penetrating a portion of the second front surface cover layer; and at least one first bonded pad penetrating the first rear surface cover layer and the second front surface cover layer.