US Patent Application 18355222. MEMORY ADDRESS PROTECTION CIRCUIT AND METHOD OF OPERATING SAME simplified abstract

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MEMORY ADDRESS PROTECTION CIRCUIT AND METHOD OF OPERATING SAME

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.


Inventor(s)

Saman M. I. Adham of Hsinchu (TW)

Ramin Shariat-yazdi of Hsinchu (TW)

Shih-Lien Linus Lu of Hsinchu (TW)

MEMORY ADDRESS PROTECTION CIRCUIT AND METHOD OF OPERATING SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 18355222 titled 'MEMORY ADDRESS PROTECTION CIRCUIT AND METHOD OF OPERATING SAME

Simplified Explanation

The patent application describes a memory circuit that includes various components to ensure data integrity and address accuracy.

  • The memory circuit stores a data unit and parity bits, which include data parity bits and write address parity bits.
  • The write address port receives the write address associated with the stored data unit.
  • A first decoding circuit determines if there is a data error by comparing the stored data unit and data parity bits.
  • A second decoding circuit generates a decoded write address using a read address and the write address parity bits.
  • An error detecting circuit compares the decoded write address to the read address to determine if there is an address error.


Original Abstract Submitted

A memory circuit includes: a memory configured to store a data unit and parity bits, the parity bits including data parity bits based on the data unit and write address parity bits based on a write address associated with the stored data unit; a write address port configured to receive the write address for the stored data unit; a first decoding circuit configured to determine when a data error exists based on the stored data unit and the data parity bits; a second decoding circuit configured to generate a decoded write address from a read address and the write address parity bits; and an error detecting circuit configured to determine when an address error exists based on a comparison of the decoded write address to the read address.

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