US Patent Application 18350738. METHOD OF MANUFACTURING INTEGRATED CIRCUIT HAVING THROUGH-SUBSTRATE VIA simplified abstract

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METHOD OF MANUFACTURING INTEGRATED CIRCUIT HAVING THROUGH-SUBSTRATE VIA

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.


Inventor(s)

Chih-Chia Hu of Taipei (TW)

Ming-Fa Chen of Taichung City (TW)

Sen-Bor Jan of Tainan City (TW)

Meng-Wei Chiang of Hsinchu (TW)

METHOD OF MANUFACTURING INTEGRATED CIRCUIT HAVING THROUGH-SUBSTRATE VIA - A simplified explanation of the abstract

This abstract first appeared for US patent application 18350738 titled 'METHOD OF MANUFACTURING INTEGRATED CIRCUIT HAVING THROUGH-SUBSTRATE VIA

Simplified Explanation

The patent application describes a method for generating an integrated circuit (IC) layout design and manufacturing an IC based on the design.

  • The IC layout design includes patterns of shallow trench isolation (STI) regions and through substrate vias (TSV) within the STI region.
  • The layout design also includes a second STI region surrounding the first STI region, with a first and second layout region separated by a first layout region.
  • The first layout region defines dummy devices, while the second layout region defines active devices.
  • The first active regions within the first layout region have identical dimensions in a specific direction.
  • The method allows for efficient and organized layout design of ICs, optimizing the use of space and improving manufacturing processes.


Original Abstract Submitted

A method includes generating an integrated circuit (IC) layout design and manufacturing an IC based on the IC layout design. Generating the IC layout design includes generating a pattern of a first shallow trench isolation (STI) region and a pattern of a through substrate via (TSV) region within the first STI region; a pattern of a second STI region surrounding the first STI region, the second STI region includes a first and second layout region, the second layout region being separated from the first STI region by the first layout region, first active regions of a group of dummy devices being defined within the first layout region, and second active regions of a group of active devices being defined within the second layout region; and patterns of first gates of the group of dummy devices in the first layout region, each of the first active regions having substantially identical dimension in a first direction.

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