US Patent Application 18341880. CHIP STACKING STRUCTURE AND MANUFACTURING METHOD THEREOF, CHIP PACKAGE STRUCTURE, AND ELECTRONIC DEVICE simplified abstract
CHIP STACKING STRUCTURE AND MANUFACTURING METHOD THEREOF, CHIP PACKAGE STRUCTURE, AND ELECTRONIC DEVICE
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CHIP STACKING STRUCTURE AND MANUFACTURING METHOD THEREOF, CHIP PACKAGE STRUCTURE, AND ELECTRONIC DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18341880 titled 'CHIP STACKING STRUCTURE AND MANUFACTURING METHOD THEREOF, CHIP PACKAGE STRUCTURE, AND ELECTRONIC DEVICE
Simplified Explanation
The patent application describes a chip stacking structure with multiple chips stacked sequentially.
- The structure includes a first redistribution layer on the active side of each chip.
- The outermost chips have their passive sides facing outward.
- A second redistribution layer is arranged on the passive side of either the first or second chip.
- The second redistribution layer is electrically connected to at least one first redistribution layer through a via hole.
Original Abstract Submitted
A chip stacking structure includes a plurality of chips that are sequentially stacked and a first redistribution layer arranged on an active side of each chip. The plurality of chips include a first chip and a second chip that are located on an outermost side. Passive sides of the first chip and the second chip both face an outer side, and the chip stacking structure further includes a second redistribution layer arranged on the passive side of the first chip or the second chip. The second redistribution layer is electrically connected to at least one first redistribution layer through a first via hole.
