US Patent Application 18341332. Semiconductor Devices simplified abstract
Contents
Semiconductor Devices
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Yu-Lien Huang of Jhubei City (TW)
Ching-Feng Fu of Taichung City (TW)
Semiconductor Devices - A simplified explanation of the abstract
This abstract first appeared for US patent application 18341332 titled 'Semiconductor Devices
Simplified Explanation
The patent application describes a method for fabricating a semiconductor device.
- The method involves forming a gate stack and growing a source/drain region adjacent to the channel region.
- A first ILD layer is deposited over the source/drain region and the gate stack.
- Source/drain and gate contacts are formed through the first ILD layer to physically contact the source/drain region and the gate stack, respectively.
- An etching process is performed to partially expose the sidewalls at the interfaces of the contacts and the first ILD layer.
- First and second conductive features are formed to physically contact the exposed sidewalls and the top surfaces of the contacts, respectively.
Original Abstract Submitted
An embodiment method includes: forming a gate stack over a channel region; growing a source/drain region adjacent the channel region; depositing a first ILD layer over the source/drain region and the gate stack; forming a source/drain contact through the first ILD layer to physically contact the source/drain region; forming a gate contact through the first ILD layer to physically contact the gate stack; performing an etching process to partially expose a first sidewall and a second sidewall, the first sidewall being at a first interface of the source/drain contact and the first ILD layer, the second sidewall being at a second interface of the gate contact and the first ILD layer; forming a first conductive feature physically contacting the first sidewall and a first top surface of the source/drain contact; and forming a second conductive feature physically contacting the second sidewall and a second top surface of the gate contact.
