US Patent Application 18338893. Multi-Phase Clock Generation Circuit simplified abstract
Contents
Multi-Phase Clock Generation Circuit
Organization Name
Inventor(s)
Theng Tee Yeo of Singapore (SG)
Multi-Phase Clock Generation Circuit - A simplified explanation of the abstract
- This abstract for appeared for US patent application number 18338893 Titled 'Multi-Phase Clock Generation Circuit'
Simplified Explanation
The abstract describes a circuit that generates multiple non-overlapping clock signals. The circuit includes a loop structure made up of logic gates, where the input and output ends of the gates are connected in a loop. There are also latches that store signals at the input ends of the gates. The circuit performs logical operations based on selection signals and clock signals, and it latches data from previous stages of the circuit. The output of the circuit is multiple non-overlapping clock signals.
Original Abstract Submitted
A multi-phase clock generation circuit is configured to generate a multi-phase non-overlapping clock signal and includes a loop structure, where input ends and output ends of a plurality of logic gates are electrically coupled head to tail to form the loop structure; and a plurality of latches configured to latch signals at the input ends of the logic gates. The multi-phase clock generation circuit performs a logical operation based on selection signals and clock signals that are received at the logic gates, latches data of upper-stage logic gates that is received at logic gates in a loop through the latches, and outputs multi-phase non-overlapping clock signals through the output ends of the logic gates.
