US Patent Application 18333886. SEMICONDUCTOR MEMORY DEVICES HAVING STACKED STRUCTURES THEREIN THAT SUPPORT HIGH INTEGRATION simplified abstract

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SEMICONDUCTOR MEMORY DEVICES HAVING STACKED STRUCTURES THEREIN THAT SUPPORT HIGH INTEGRATION

Inventors

Sangjae Lee of Busan (KR)


Jaehyung Kim of Seoul (KR)


Dongseog Eun of Seongnam-si (KR)


SEMICONDUCTOR MEMORY DEVICES HAVING STACKED STRUCTURES THEREIN THAT SUPPORT HIGH INTEGRATION - A simplified explanation of the abstract

  • This abstract for appeared for patent application number 18333886 Titled 'SEMICONDUCTOR MEMORY DEVICES HAVING STACKED STRUCTURES THEREIN THAT SUPPORT HIGH INTEGRATION'

Simplified Explanation

This abstract describes a semiconductor device that consists of multiple layers stacked on top of each other. The device includes a channel structure that runs through these layers. The lower stack structure has two layers of electrodes - a first layer located at the interface between the lower and upper stack structures, and a second layer in the center of the lower stack structure. Similarly, the upper stack structure also has two layers of electrodes - a first layer at the interface and a second layer in the center. The first layer of either the lower or upper electrodes is thicker than the second layer. Additionally, there is at least one insulating layer between the first layer of the lower electrode and the first layer of the upper electrode.


Original Abstract Submitted

A semiconductor device includes an upper stack structure extending on a lower stack structure, which extends on an underlying substrate. A channel structure extends through the upper stack structure and the lower stack structure. The lower stack structure includes a first lower electrode layer disposed adjacent to an interface between the lower stack structure and the upper stack structure, and a second lower electrode layer disposed adjacent a center of the lower stack structure. The upper stack structure includes a first upper electrode layer disposed adjacent to the interface, and a second upper electrode layer disposed adjacent a center of the upper stack structure. At least one of the first lower electrode layer and the first upper electrode layer is thicker than the second lower electrode layer. At least one insulating layer is disposed between the first lower electrode layer and the first upper electrode layer.

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