US Patent Application 18307098. SEMICONDUCTOR MEMORY DEVICE AND MEMORY simplified abstract
Contents
SEMICONDUCTOR MEMORY DEVICE AND MEMORY
Organization Name
Inventor(s)
Jun Young Park of Suwon-si (KR)
Eun Seok Shin of Suwon-si (KR)
Hyun-Yoon Cho of Suwon-si (KR)
Jung Hwan Choi of Suwon-si (KR)
SEMICONDUCTOR MEMORY DEVICE AND MEMORY - A simplified explanation of the abstract
This abstract first appeared for US patent application 18307098 titled 'SEMICONDUCTOR MEMORY DEVICE AND MEMORY
Simplified Explanation
The patent application describes a semiconductor memory device with various components for clock signal adjustment and error detection.
- The device includes a data clock buffer that receives a data clock signal and outputs a pair of differential input signals.
- An edge delay controller adjusts the duty ratios of the input signals based on a control code and outputs a pair of corrected clock signals.
- A first unit delay path circuit generates four output clock signals with different phases based on the corrected clock signals.
- A rising edge multiplexer serially outputs data corresponding to the rising edge of each of the four output clock signals.
- A second unit delay path circuit generates four duplicate clock signals with different phases based on the corrected clock signals.
- A quadrature error correction circuit detector detects a duty error based on the duplicate clock signals and outputs the control code.
Original Abstract Submitted
A semiconductor memory device is provided. The semiconductor includes a data clock buffer that receives a data clock signal from a memory controller and outputs a pair of differential input signals, an edge delay controller that adjusts duty ratios of the pair of differential input signals based on a control code and outputs a pair of corrected clock signals, a first unit delay path circuit that generates four output clock signals having different phases based on the pair of corrected clock signals, a rising edge multiplexer that serially outputs data corresponding to a rising edge of each of the four output clock signals, a second unit delay path circuit that generates four duplicate clock signals having different phases based on the pair of corrected clock signals and a quadrature error correction circuit detector that detects a duty error based on the duplicate clock signals and outputs the control code.
