US Patent Application 18306087. Transaction Generator for On-chip Interconnect Fabric simplified abstract
Contents
Transaction Generator for On-chip Interconnect Fabric
Organization Name
Inventor(s)
Charles J. Fleckenstein of Portland OR (US)
Lital Levy-rubin of Tel Aviv (IL)
Transaction Generator for On-chip Interconnect Fabric - A simplified explanation of the abstract
- This abstract for appeared for US patent application number 18306087 Titled 'Transaction Generator for On-chip Interconnect Fabric'
Simplified Explanation
The abstract describes a system-on-chip (SOC) that has a global communication fabric consisting of multiple independent networks with different communication protocols. The SOC also includes several input-output (I/O) clusters, each with a different set of local functional circuits. Each I/O cluster can be connected to one or more of the independent networks and has a local fabric, an interface circuit, and a programmable hardware transaction generator circuit. The interface circuit facilitates communication between the local functional circuits and the global communication fabric. The programmable hardware transaction generator circuit can create test transactions to simulate interactions between the local functional circuits and a specific independent network.
Original Abstract Submitted
In an embodiment, an SOC includes a global communication fabric that includes multiple independent networks having different communication and coherency protocols, and a plurality of input-output (I/O) clusters that includes different sets of local functional circuits. A given I/O cluster may be coupled to one or more of the independent networks and may include a particular set of local functional circuits, a local fabric coupled to the particular set of local functional circuits, and an interface circuit coupled to the local fabric and configured to bridge transactions between the particular set of local functional circuits and the global communication fabric. The interface circuit may include a programmable hardware transaction generator circuit configured to generate a set of test transactions that simulate interactions between the particular set of local functional circuits and a particular one of the one or more independent networks.
