US Patent Application 18299452. SIMD Operand Permutation with Selection from among Multiple Registers simplified abstract

SIMD Operand Permutation with Selection from among Multiple Registers

Inventors

Christopher A. Burns of Austin TX (US)

Liang-Kai Wang of Austin TX (US)

Robert D. Kenney of Austin TX (US)

Terence M. Potter of Austin TX (US)

SIMD Operand Permutation with Selection from among Multiple Registers - A simplified explanation of the abstract

• This abstract for appeared for patent application number 18299452 Titled 'SIMD Operand Permutation with Selection from among Multiple Registers'

Simplified Explanation

This abstract describes techniques for routing operands among Single-Instruction Multiple-Data (SIMD) pipelines. The apparatus includes multiple hardware pipelines that can execute SIMD instructions for multiple threads simultaneously. These instructions specify two architectural registers. The pipelines have execution circuitry to perform operations and routing circuitry to select the first input operand for the execution circuitry. The routing circuitry can choose between a value from the first architectural register of another pipeline and a value from the second architectural register of a thread assigned to another pipeline. Additionally, the routing circuitry can support a shift and fill instruction, which allows for storing a specific portion of a graphics frame in one or more registers.

Original Abstract Submitted

Techniques are disclosed relating to operand routing among SIMD pipelines. In some embodiments, an apparatus includes a set of multiple hardware pipelines configured to execute a single-instruction multiple-data (SIMD) instruction for multiple threads in parallel, wherein the instruction specifies first and second architectural registers. In some embodiments, the pipelines include execution circuitry configured to perform operations using one or more pipeline stages of the pipeline. In some embodiments, the pipelines include routing circuitry configured to select, based on the instruction, a first input operand for the execution circuitry from among: a value from the first architectural register from thread-specific storage for another pipeline and a value from the second architectural register from thread-specific storage for a thread assigned to another pipeline. In some embodiments, the routing circuitry may support a shift and fill instruction that facilitates storage of an arbitrary portion of a graphics frame in one or more registers.