US Patent Application 18232768. CIRCUITS AND METHODS FOR COMPENSATING A MISMATCH IN A SENSE AMPLIFIER simplified abstract
Contents
CIRCUITS AND METHODS FOR COMPENSATING A MISMATCH IN A SENSE AMPLIFIER
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Ku-Feng Lin of New Taipei City (TW)
Yu-Der Chih of Hsin-Chu City (TW)
Chia-Fu Lee of Hsinchu City (TW)
CIRCUITS AND METHODS FOR COMPENSATING A MISMATCH IN A SENSE AMPLIFIER - A simplified explanation of the abstract
This abstract first appeared for US patent application 18232768 titled 'CIRCUITS AND METHODS FOR COMPENSATING A MISMATCH IN A SENSE AMPLIFIER
Simplified Explanation
The patent application describes circuits and methods for compensating mismatches in sense amplifiers.
- The circuit includes a first branch and a second branch.
- The first branch consists of a first transistor, a second transistor, and a first node.
- The second branch consists of a third transistor, a fourth transistor, and a second node.
- The first node is connected to the gates of the third and fourth transistors.
- The second node is connected to the gates of the first and second transistors.
- A first plurality of trimming transistors is connected in parallel to the second transistor.
- A second plurality of trimming transistors is connected in parallel to the fourth transistor.
Original Abstract Submitted
Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.
