US Patent Application 18232713. Semiconductor Devices With Backside Power Distribution Network And Frontside Through Silicon Via simplified abstract

Semiconductor Devices With Backside Power Distribution Network And Frontside Through Silicon Via

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Kam-Tou Sio of Zhubei City (TW)

Cheng-Chi Chuang of New Taipei City (TW)

Chia-Tien Wu of Taichung City (TW)

Jiann-Tyng Tzeng of Hsinchu (TW)

Shih-Wei Peng of Hsinchu City (TW)

Wei-Cheng Lin of Taichung City (TW)

Semiconductor Devices With Backside Power Distribution Network And Frontside Through Silicon Via - A simplified explanation of the abstract

This abstract first appeared for US patent application 18232713 titled 'Semiconductor Devices With Backside Power Distribution Network And Frontside Through Silicon Via

Simplified Explanation

The patent application describes a semiconductor structure with a power distribution network and various interlayer dielectrics and interconnect layers.

• The structure includes first and second conductive lines for power distribution.
• The substrate of the structure has a first surface in contact with the power distribution network.
• Backside vias are present in the substrate and connected to the first conductive line.
• A via rail is located on the opposite surface of the substrate.
• The structure includes multiple interlayer dielectrics, including a first, second, and third interlayer dielectric.
• The first interlayer dielectric is on the via rail and substrate.
• The second interlayer dielectric is on top of the first interlayer dielectric.
• The third interlayer dielectric is on top of the second interlayer dielectric.
• The second and third interlayer dielectrics contain first and top interconnect layers, respectively.
• Deep vias are present in the interlayer dielectric and connected to the via rail.
• The deep vias are also connected to the first and top interconnect layers.
• A power supply in/out layer is located on the third interlayer dielectric and in contact with the top interconnect layer.

Original Abstract Submitted

The present disclosure describes a semiconductor structure having a power distribution network including first and second conductive lines. A substrate includes a first surface that is in contact with the power distribution network. A plurality of backside vias are in the substrate and electrically coupled to the first conductive line. A via rail is on a second surface of the substrate that opposes the first surface. A first interlayer dielectric is on the via rail and on the substrate. A second interlayer dielectric is on the first interlayer dielectric. A third interlayer dielectric is on the second interlayer dielectric. First and top interconnect layers are in the second and third interlayer dielectrics, respectively. Deep vias are in the interlayer dielectric and electrically coupled to the via rail. The deep vias are also connected to the first and top interconnect layers. A power supply in/out layer is on the third interlayer dielectric and in contact with the top interconnect layer.