US Patent Application 18232520. SEMICONDUCTOR PACKAGE INCLUDING TEST LINE STRUCTURE simplified abstract

SEMICONDUCTOR PACKAGE INCLUDING TEST LINE STRUCTURE

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.==Inventor(s)==

[[Category:Tsung-Yang Hsieh of Taipei City (TW)]]

[[Category:Chien-Chang Lee of Miaoli County (TW)]]

[[Category:Chia-Ping Lai of Hsinchu City (TW)]]

[[Category:Wen-Chung Lu of Hsinchu (TW)]]

[[Category:Cheng-Kang Huang of Hsinchu (TW)]]

[[Category:Mei-Shih Kuo of Hsinchu (TW)]]

[[Category:Alice Huang of Hsinchu (TW)]]

SEMICONDUCTOR PACKAGE INCLUDING TEST LINE STRUCTURE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18232520 titled 'SEMICONDUCTOR PACKAGE INCLUDING TEST LINE STRUCTURE

Simplified Explanation

- The patent application describes a package that includes an interposer and a die device structure. - The interposer has an interposer substrate with at least one layer and multiple RDLs (Redistribution Layers) formed through the substrate. - The die device structure includes at least one device die. - A first test line (TL) structure is placed between the interposer and the die device structure. - The first TL structure includes at least one test line that is electrically connected to the device die. - The test line extends beyond the edge of the die device structure to create an electrical interface with the device die. - The purpose of this innovation is to provide a simplified and efficient electrical connection between the interposer and the device die.

Original Abstract Submitted

A package comprises an interposer, comprising an interposer substrate including at least one layer, and a plurality of RDLs formed through at least a portion of the interposer substrate. The package also includes a die device structure comprising at least one device die, and a first test line (TL) structure interposed between the interposer and the die device structure. The first TL structure includes at least one first test line electrically coupled to the at least one device die, at least a portion of the at least one first test line extending beyond a peripheral edge of the die device structure to provide an electrical interface with the at least one device die.