US Patent Application 18232336. METHOD AND APPARATUS FOR LOGIC CELL-BASED PUF GENERATORS simplified abstract

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METHOD AND APPARATUS FOR LOGIC CELL-BASED PUF GENERATORS

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Shih-Lien Linus Lu of Hsinchu City (TW)

Cormac Michael O'connell of Kanata CA (US)

METHOD AND APPARATUS FOR LOGIC CELL-BASED PUF GENERATORS - A simplified explanation of the abstract

This abstract first appeared for US patent application 18232336 titled 'METHOD AND APPARATUS FOR LOGIC CELL-BASED PUF GENERATORS

Simplified Explanation

The patent application describes a physical unclonable function (PUF) generator circuit and testing method.

  • The PUF generator includes a PUF cell array with multiple bit cells arranged in columns and rows.
  • Each column is connected to at least two pre-discharge transistors, and each bit cell has enable transistors, access transistors, and storage nodes.
  • A PUF control circuit is connected to the PUF cell array and is responsible for pre-charging the storage nodes with the same voltages to establish a first logical state.
  • The control circuit then determines a second logical state based on the voltages of the storage nodes in each bit cell.
  • Using the determined second logical states, the control circuit generates a PUF signature.


Original Abstract Submitted

Disclosed is a physical unclonable function generator circuit and testing method. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, wherein each of the plurality of columns is coupled to at least two pre-discharge transistors, and each of the plurality of bit cells comprises at least one enable transistor, at least two access transistors, and at least two storage nodes, and a PUF control circuit coupled to the PUF cell array, wherein the PUF control circuit is configured to access the plurality of bit cells to pre-charge the at least two storage nodes with substantially the same voltages allowing each of the plurality of bit cell having a first metastable logical state; to determine a second logical state; and based on the determined second logical states of the plurality of bit cells, to generate a PUF signature.

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