US Patent Application 18230829. Method of Forming Semiconductor Packages Having Through Package Vias simplified abstract
Contents
Method of Forming Semiconductor Packages Having Through Package Vias
Organization Name
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s)
Chih-Wei Lin of Zhubei City (TW)
Ming-Da Cheng of Jhubei City (TW)
Method of Forming Semiconductor Packages Having Through Package Vias - A simplified explanation of the abstract
This abstract first appeared for US patent application 18230829 titled 'Method of Forming Semiconductor Packages Having Through Package Vias
Simplified Explanation
- The patent application describes a semiconductor device and a method for forming the device. - The device includes an integrated circuit with through vias located next to the integrated circuit die. - A molding compound is placed between the integrated circuit die and the through vias. - The through vias have a projection that extends through a patterned layer. - The through vias may be offset from the surface of the patterned layer. - The recess in the through vias is created by selectively removing a seed layer used to form them.
Original Abstract Submitted
A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.
