US Patent Application 18230546. SEMICONDUCTOR PACKAGES AND METHODS FOR FORMING THE SAME simplified abstract
Contents
SEMICONDUCTOR PACKAGES AND METHODS FOR FORMING THE SAME
Organization Name
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s)
Shin-Yi Yang of New Taipei (TW)
SEMICONDUCTOR PACKAGES AND METHODS FOR FORMING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18230546 titled 'SEMICONDUCTOR PACKAGES AND METHODS FOR FORMING THE SAME
Simplified Explanation
The patent application describes an integrated circuit die with vertical interconnect features for connecting vertically stacked integrated circuit dies.
- The vertical interconnect features are located in a sealing ring, allowing for higher routing density compared to other methods such as interposers or redistribution layers.
- This direct connection between vertically stacked integrated circuit dies reduces the need for interposer layers, redistribution processes, and bumping processes, resulting in lower manufacturing costs.
Original Abstract Submitted
Embodiments of the present disclosure provide an integrated circuit die with vertical interconnect features to enable direct connection between vertically stacked integrated circuit dies. The vertical interconnect features may be formed in a sealing ring, which allows higher routing density than interposers or redistribution layer. The direct connection between vertically stacked integrated circuit dies reduces interposer layers, redistribution process, and bumping processes in multi-die integration, thus, reducing cost of manufacturing.
