US Patent Application 18227744. GATE STRUCTURES FOR SEMICONDUCTOR DEVICES simplified abstract
Contents
GATE STRUCTURES FOR SEMICONDUCTOR DEVICES
Organization Name
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s)
Chung-Liang Cheng of Changhua County (TW)
GATE STRUCTURES FOR SEMICONDUCTOR DEVICES - A simplified explanation of the abstract
This abstract first appeared for US patent application 18227744 titled 'GATE STRUCTURES FOR SEMICONDUCTOR DEVICES
Simplified Explanation
The abstract describes a semiconductor device with different gate structures that can achieve ultra-low threshold voltages. The device includes nanostructured channel regions and gate-all-around (GAA) structures.
- The semiconductor device has first and second nanostructured channel regions in different layers.
- The first GAA structure surrounding the first nanostructured channel region includes an Al-based gate stack with multiple layers.
- The second GAA structure surrounding the second nanostructured channel region includes an Al-free gate stack with multiple layers.
- The different gate structures allow for ultra-low threshold voltages in the semiconductor device.
- The fabrication method for the semiconductor device is also disclosed.
Original Abstract Submitted
The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes first and second nanostructured channel regions in first and second nanostructured layers, respectively, and first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The first GAA structure includes an Al-based gate stack with a first gate dielectric layer, an Al-based n-type work function metal layer, a first metal capping layer, and a first gate metal fill layer. The second GAA structure includes an Al-free gate stack with a second gate dielectric layer, an Al-free p-type work function metal layer, a metal growth inhibition layer, a second metal capping layer, and a second gate metal fill layer.
