US Patent Application 18227726. ELECTRON MIGRATION CONTROL IN INTERCONNECT STRUCTURES simplified abstract

ELECTRON MIGRATION CONTROL IN INTERCONNECT STRUCTURES

Organization Name

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor(s)

Chun-Jen Chen of Hsinchu (TW)

Kai-Shiung Hsu of Hsinchu City 300 (TW)

Ding-I Liu of Hsinchu City 300 (TW)

Jyh-nan Lin of Hsinchu City 300 (TW)

ELECTRON MIGRATION CONTROL IN INTERCONNECT STRUCTURES - A simplified explanation of the abstract

This abstract first appeared for US patent application 18227726 titled 'ELECTRON MIGRATION CONTROL IN INTERCONNECT STRUCTURES

Simplified Explanation

The patent application describes a method for improving the reliability of interconnect structures in semiconductor devices.

• The method involves forming a contact structure on a transistor and then forming a metallization layer on top of the contact structure.
• To form the metallization layer, an inter-metal dielectric (IMD) layer is first deposited on the transistor.
• An opening is then created within the IMD layer to expose the top surface of the contact structure.
• A metallic layer is deposited to fill the opening, and an electron barrier layer is formed within the IMD layer.
• Finally, a capping layer is formed within the metallic layer.

The key innovation lies in the composition of the electron barrier layer and the capping layer:

• The electron barrier layer has a higher hole carrier concentration compared to a portion of the IMD layer underneath it.
• The capping layer also has a higher hole carrier concentration compared to a portion of the metallic layer underneath it.

These higher hole carrier concentrations in the electron barrier layer and capping layer help to improve the reliability of the interconnect structures in the semiconductor devices.

Original Abstract Submitted

A method for improving reliability of interconnect structures for semiconductor devices is disclosed. The method includes forming a contact structure on a transistor and forming a metallization layer on the contact structure. The forming the metallization layer includes depositing an inter-metal dielectric (IMD) layer on the transistor, forming an opening within the IMD layer to expose a top surface of the contact structure, depositing a metallic layer to fill the opening, forming an electron barrier layer within the IMD layer, and forming a capping layer within the metallic layer. The electron barrier layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the IMD layer underlying the electron barrier layer. The capping layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the metallic layer underlying the capping layer.