US Patent Application 18227712. SPACER STRUCTURES FOR SEMICONDUCTOR DEVICES simplified abstract

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SPACER STRUCTURES FOR SEMICONDUCTOR DEVICES

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Cheng-Yi Peng of Taipei City 112 (TW)

Song-Bor Lee of Zhubei City (TW)

SPACER STRUCTURES FOR SEMICONDUCTOR DEVICES - A simplified explanation of the abstract

This abstract first appeared for US patent application 18227712 titled 'SPACER STRUCTURES FOR SEMICONDUCTOR DEVICES

Simplified Explanation

The patent application describes a semiconductor device structure and a method of fabricating it.

  • The semiconductor device includes a substrate, nanostructured layers, and source/drain (S/D) regions.
  • The S/D regions have an epitaxial region wrapped around the nanostructured regions.
  • The device also includes a gate-all-around (GAA) structure wrapped around the nanostructured regions.
  • Inner spacers are placed between the S/D regions and the GAA structure.
  • A passivation layer is applied to the sidewalls of the nanostructured regions.
  • The innovation improves the performance and efficiency of the semiconductor device.


Original Abstract Submitted

The structure of a semiconductor device with inner spacer structures between source/drain (S/D) regions and gate-all-around structures and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a stack of nanostructured layers with first and second nanostructured regions disposed on the substrate and first and second source/drain (S/D) regions disposed on the substrate. Each of the first and second S/D regions includes an epitaxial region wrapped around each of the first nanostructured regions. The semiconductor device further includes a gate-all-around (GAA) structure disposed between the first and second S/D regions and wrapped around each of the second nanostructured regions, a first inner spacer disposed between an epitaxial sub-region of the first S/D region and a gate sub-region of the GAA structure, a second inner spacer disposed between an epitaxial sub-region of the second S/D region and the gate sub-region of the GAA structure, and a passivation layer disposed on sidewalls of the first and second nanostructured regions

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