US Patent Application 18225028. METHOD OF FORMING MULTIPLE-VT FETS FOR CMOS CIRCUIT APPLICATIONS simplified abstract

METHOD OF FORMING MULTIPLE-VT FETS FOR CMOS CIRCUIT APPLICATIONS

Organization Name

Samsung Electronics Co., Ltd.

Inventor(s)

Wei-E Wang of Austin TX (US)

Mark S. Rodder of Dallas TX (US)

METHOD OF FORMING MULTIPLE-VT FETS FOR CMOS CIRCUIT APPLICATIONS - A simplified explanation of the abstract

This abstract first appeared for US patent application 18225028 titled 'METHOD OF FORMING MULTIPLE-VT FETS FOR CMOS CIRCUIT APPLICATIONS

Simplified Explanation

The abstract describes a field-effect transistor (FET) device with a modulated threshold voltage (Vt).

• The FET device includes a source electrode, a drain electrode, a channel region, and a gate stack.
• The gate stack consists of an ultrathin dielectric dipole layer, a high-k (HK) insulating layer, and a gate metal layer.
• The ultrathin dielectric dipole layer is designed to shift the modulated threshold voltage in a first direction.
• The HK insulating layer is placed on top of the ultrathin dielectric dipole layer.
• The gate metal layer is then added on top of the HK insulating layer to shift the modulated threshold voltage in a second direction.

Original Abstract Submitted

A field-effect transistor (FET) device having a modulated threshold voltage (Vt) includes a source electrode, a drain electrode, a channel region extending between the source electrode and the drain electrode, and a gate stack on the channel region. The gate stack includes an ultrathin dielectric dipole layer configured to shift the modulated Vt in a first direction, a high-k (HK) insulating layer on the ultrathin dielectric dipole layer, and a gate metal layer on the HK insulating layer configured to shift the modulated Vt in a second direction.