US Patent Application 18214172. SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME simplified abstract
Contents
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
Organization Name
Inventor(s)
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A simplified explanation of the abstract
- This abstract for appeared for US patent application number 18214172 Titled 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME'
Simplified Explanation
The abstract describes a semiconductor package that consists of two packages stacked on top of each other. The first package contains two semiconductor chips and a core member with a hole. One of the chips is placed inside the hole. An encapsulant is filled in the hole. A redistribution layer is placed above the core member and connects the chips. Another redistribution layer is placed below the core member and connects the chips to an external printed circuit board (PCB). Core vias penetrate the core member and connect the two redistribution layers. The second package is placed on top of the first package and contains a third semiconductor chip. Electrical connection structures connect the first and second packages, and additional electrical connection structures connect the semiconductor package to the external PCB.
Original Abstract Submitted
A semiconductor package includes a first package having a first semiconductor chip, a second semiconductor chip and a core member including a through-hole. At least one of the first and second semiconductor chips is disposed in the through-hole. An encapsulant is disposed in the through-hole. A first redistribution layer is disposed above the core member and is electrically connected to the first and second semiconductor chips. A second redistribution layer is disposed under the core member and electrically connects the first and second semiconductor chips with an external PCB. Core vias penetrate the core member and electrically connect the first and second redistribution layers. A second package is disposed on the first package and includes a third semiconductor chip. A plurality of first electrical connection structures electrically connects the first and second packages. A plurality of second electrical connection structures electrically connects the semiconductor package with the external PCB.
