US Patent Application 18208127. TRANSCEIVER AND METHOD OF DRIVING THE SAME simplified abstract
Contents
TRANSCEIVER AND METHOD OF DRIVING THE SAME
Inventors
Dong Won Park of Yongin-si (KR)
Kyung Youl Min of Yongin-si (KR)
Jong Man Bae of Yongin-si (KR)
Jun Yong Song of Yongin-si (KR)
Tae Young Jin of Yongin-si (KR)
TRANSCEIVER AND METHOD OF DRIVING THE SAME - A simplified explanation of the abstract
- This abstract for appeared for US patent application number 18208127 Titled 'TRANSCEIVER AND METHOD OF DRIVING THE SAME'
Simplified Explanation
This abstract describes a transceiver, which is a device that can both transmit and receive signals. The transceiver consists of a transmitter and a receiver that are connected to each other through two lines.
In the first mode, the transmitter sends signals with a certain voltage range to both lines. In the second mode, it sends signals with a lower voltage range to the lines.
When transmitting a specific payload to the receiver, the transmitter operates in a sequence of the first mode, the second mode, and then the first mode again. It sends a clock training pattern and the payload in the second mode.
The receiver includes a clock data recovery circuit, which generates a clock signal based on the received clock training pattern. It also has a register that stores frequency and phase information of the clock training pattern.
Original Abstract Submitted
A transceiver includes a transmitter and a receiver connected to each other through a first line and a second line. The transmitter transmits signals having a first voltage range to the first line and the second line in a first mode, and transmits signals having a second voltage range less than the first voltage range to the first line and the second line in a second mode. In transmitting a (1−1)-th payload to the receiver, the transmitter is sequentially driven in the first mode, the second mode, and the first mode, and transmits a first clock training pattern and the (1−1)-th payload in the second mode. The receiver includes a clock data recovery circuit generating a first clock signal corresponding to the received first clock training pattern and a register storing first frequency information and first phase information of the first clock training pattern.
