US Patent Application 18178105. EFFICIENT CACHE PROGRAM OPERATION WITH DATA ENCODING simplified abstract
Contents
EFFICIENT CACHE PROGRAM OPERATION WITH DATA ENCODING
Organization Name
Inventor(s)
Sushanth Bhushan of Boise ID (US)
Dheeraj Srinivasan of San Jose CA (US)
EFFICIENT CACHE PROGRAM OPERATION WITH DATA ENCODING - A simplified explanation of the abstract
- This abstract for appeared for US patent application number 18178105 Titled 'EFFICIENT CACHE PROGRAM OPERATION WITH DATA ENCODING'
Simplified Explanation
The abstract describes a memory device that uses control logic to program a set of memory cells to specific levels. It generates signals to indicate when the host system should send data for programming operations to the memory device's input/output (I/O) data cache. It also generates encoded data values for each memory cell. The abstract mentions the use of multiple cache storage areas, including an I/O data cache and a third data cache. The generated signals inform the host system when to send data for the next programming operation to the I/O data cache. Overall, the abstract highlights the process of programming memory cells and managing data storage in the memory device.
Original Abstract Submitted
Control logic in a memory device executes a first programming operation to program the set of memory cells to a set of programming levels. A first cache ready signal is generated, the first cache ready signal indicating to a host system to send first data associated with a second programming operation to an input/output (I/O) data cache of the memory device. A first encoded data value and a second encoded data value associated with each memory cell of the set of memory cells are generated. A second cache ready signal is generated, the second cache ready signal indicating to the host system to send second data associated with the next programming operation to the I/O data cache. The first data associated with the second programming operation is caused to be stored in a third data cache of the cache storage. A third cache ready signal is generated, the third cache ready signal indicating to the host system to send third data associated with the second programming operation to the I/O data cache.
