US Patent Application 18161757. TECHNIQUES FOR FOUR CYCLE ACCESS COMMANDS simplified abstract

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TECHNIQUES FOR FOUR CYCLE ACCESS COMMANDS

Organization Name

Micron Technology, Inc.


Inventor(s)

Sujeet V. Ayyapureddi of Boise ID (US)


TECHNIQUES FOR FOUR CYCLE ACCESS COMMANDS - A simplified explanation of the abstract

  • This abstract for appeared for US patent application number 18161757 Titled 'TECHNIQUES FOR FOUR CYCLE ACCESS COMMANDS'

Simplified Explanation

This abstract describes methods, systems, and devices for four cycle access commands. It explains that a memory device can communicate access commands with a host device using a command-address channel and multiple data channels. The host device sends an access command that includes an operation code indicating the type of command, a first address of the memory device (the first target), and a second address of the memory device (the second target). The first address is associated with a first data channel, and the second address is associated with a second data channel. This allows the memory device and the host device to communicate first data related to the first address through the first data channel and second data related to the second address through the second data channel.


Original Abstract Submitted

Methods, systems, and devices for techniques for four cycle access commands are described. A memory device may communicate access commands with a host device over a command-address (CA) channel associated with multiple data channels. The host device may transmit an access command that includes an operation code indicating a type of the access command, a first address of the memory device that is a first target of the access command, and a second address of the memory device that is a second target of the access command. The first address may be associated with a first data channel, and the second address may be associated with a second data channel. Accordingly, the memory device and the host device may communicate first data corresponding to the first address over the first data channel and second data corresponding to the second address over the second data channel.

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