US Patent Application 18151434. TRANSISTOR, MANUFACTURING METHOD THEREOF, AND MEMORY simplified abstract

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TRANSISTOR, MANUFACTURING METHOD THEREOF, AND MEMORY

Organization Name

CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor(s)

CHUN-WEI Liao of Hefei City (CN)

Xiaoguang Wang of Hefei City (CN)

Deyuan Xiao of Hefei City (CN)

TZUNG-HAN Lee of Hefei City (CN)

TRANSISTOR, MANUFACTURING METHOD THEREOF, AND MEMORY - A simplified explanation of the abstract

This abstract first appeared for US patent application 18151434 titled 'TRANSISTOR, MANUFACTURING METHOD THEREOF, AND MEMORY

Simplified Explanation

The patent application describes a transistor design that includes several key components:

  • The transistor has a substrate with an active area.
  • It includes a gate structure that goes through the active area and consists of a gate and a gate dielectric layer.
  • The gate dielectric layer covers the sidewalls and bottom of the gate.
  • A channel layer is located on the side of the gate dielectric layer opposite the gate.
  • The channel layer contains a metal oxide semiconductor layer.
  • The active area of the transistor includes a first active layer and a second active layer on either side of the gate structure.
  • Both the first and second active layers are in contact with the channel layer.

This design aims to improve the performance and functionality of transistors by utilizing a metal oxide semiconductor layer in the channel layer and optimizing the contact between the active layers and the channel layer.


Original Abstract Submitted

A transistor includes: a substrate including an active area; a gate structure penetrating through the active area and including a gate and a gate dielectric layer, in which the gate dielectric layer covers sidewalls and a bottom of the gate; a channel layer located on a side of the gate dielectric layer away from the gate, in which the channel layer includes a metal oxide semiconductor layer, in which the active area includes a first active layer and a second active layer located at two sides of the gate structure, and the first active layer and the second active layer are in contact with the channel layer.

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