US Patent Application 18132437. WAFER LEVEL CHIP SCALE PACKAGE WITH SIDEWALL PROTECTION simplified abstract
Contents
WAFER LEVEL CHIP SCALE PACKAGE WITH SIDEWALL PROTECTION
Organization Name
Inventor(s)
Yu-Tung Chen of Hsinchu City (TW)
Pei-Haw Tsao of Hsinchu City (TW)
Kuo-Lung Fan of Hsinchu City (TW)
WAFER LEVEL CHIP SCALE PACKAGE WITH SIDEWALL PROTECTION - A simplified explanation of the abstract
This abstract first appeared for US patent application 18132437 titled 'WAFER LEVEL CHIP SCALE PACKAGE WITH SIDEWALL PROTECTION
Simplified Explanation
The patent application describes a wafer level chip scale package that includes a bare silicon die with an active surface, a rear surface, and a sidewall surface.
- The bare silicon die has a backside corner between the rear surface and the sidewall surface.
- The active surface has multiple pads, and each pad has a conductive element.
- A backside tape is attached to the rear surface using an adhesive layer.
- The adhesive layer and backside tape extend beyond the sidewall surfaces of the bare silicon die.
- The adhesive layer wraps around the backside corner of the bare silicon die.
Original Abstract Submitted
A wafer level chip scale package includes a bare silicon die having an active surface, a rear surface opposite to the active surface, and a sidewall surface between the active surface and the rear surface. The bare silicon die includes a backside corner between the rear surface and the sidewall surface. A plurality of pads is disposed on the active surface. A plurality of conductive elements is disposed on the plurality of pads, respectively. A backside tape is adhered to the rear surface by using an adhesive layer. The adhesive layer and the backside tape protrude beyond the sidewall surfaces of the bare silicon die. The adhesive layer extends along the sidewall surface and wraps around the backside corner.
