US Patent Application 18109830. INTERPOSERS FOR MEMORY DEVICE TESTING AND CHARACTERIZATION, INCLUDING INTERPOSERS FOR TESTING AND CHARACTERIZING DECISION FEEDBACK EQUALIZATION CIRCUITRY OF DDR5 MEMORY DEVICES simplified abstract

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INTERPOSERS FOR MEMORY DEVICE TESTING AND CHARACTERIZATION, INCLUDING INTERPOSERS FOR TESTING AND CHARACTERIZING DECISION FEEDBACK EQUALIZATION CIRCUITRY OF DDR5 MEMORY DEVICES

Organization Name

Micron Technology, Inc.

Inventor(s)

Eric J. Stave of Meridian ID (US)

Luis Nathan Perez Acosta of Boise ID (US)

Bryce A. Gardiner of Meridian ID (US)

INTERPOSERS FOR MEMORY DEVICE TESTING AND CHARACTERIZATION, INCLUDING INTERPOSERS FOR TESTING AND CHARACTERIZING DECISION FEEDBACK EQUALIZATION CIRCUITRY OF DDR5 MEMORY DEVICES - A simplified explanation of the abstract

This abstract first appeared for US patent application 18109830 titled 'INTERPOSERS FOR MEMORY DEVICE TESTING AND CHARACTERIZATION, INCLUDING INTERPOSERS FOR TESTING AND CHARACTERIZING DECISION FEEDBACK EQUALIZATION CIRCUITRY OF DDR5 MEMORY DEVICES

Simplified Explanation

- The patent application is about interposers used for testing and characterizing memory devices, specifically those with decision feedback equalization circuitry. - The interposer has two interfaces, one for connecting to the memory device and the other for connecting to one or more testers. - There is a channel circuit within the interposer that allows signals to be transmitted between the memory device and the testers. - The channel circuit can be configured using resistive elements to change a measurable value of the transmitted signal. - The purpose of this innovation is to provide a means for testing and characterizing memory devices more effectively and accurately.


Original Abstract Submitted

Interposers for use in testing and characterizing memory devices, such as memory devices including decision feedback equalization circuitry, are disclosed herein. In one embodiment, an apparatus includes an interposer having a first interface couplable to a memory device, a second interface couplable to one or more testers, and a channel circuit between the first interface and the second interface. The channel circuit is configurable, via one or more resistive elements, to change a measurable value of a signal transmitted between the first interface and the second interface via the channel circuit.