US Patent Application 18105815. TRANSMITTER CIRCUIT AND RECEIVER CIRCUIT OF INTERFACE CIRCUIT AND OPERATING METHOD THEREOF simplified abstract

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TRANSMITTER CIRCUIT AND RECEIVER CIRCUIT OF INTERFACE CIRCUIT AND OPERATING METHOD THEREOF

Organization Name

Samsung Electronics Co., Ltd.


Inventor(s)

BYONGMO Moon of Suwon-si (KR)

Taeryeong Kim of Seoul (KR)

Seongook Jung of Seoul (KR)

Jeonghyeok You of Seoul (KR)

TRANSMITTER CIRCUIT AND RECEIVER CIRCUIT OF INTERFACE CIRCUIT AND OPERATING METHOD THEREOF - A simplified explanation of the abstract

This abstract first appeared for US patent application 18105815 titled 'TRANSMITTER CIRCUIT AND RECEIVER CIRCUIT OF INTERFACE CIRCUIT AND OPERATING METHOD THEREOF

Simplified Explanation

The patent application describes a transmitter circuit for an interface circuit.

  • The circuit includes a clock generating circuit, a pulse generating circuit, an overlapped multiplexing circuit, and an output circuit.
  • The clock generating circuit generates multiple clocks with different phases.
  • The pulse generating circuit generates multiple pulses based on the clocks.
  • The overlapped multiplexing circuit receives multiple input signals in parallel and outputs overlapped signals based on the clocks, input signals, and pulses.
  • Each overlapped signal includes bit values from two input signals.
  • The output circuit serially outputs the bit values of the input signals based on the overlapped signals.


Original Abstract Submitted

A transmitter circuit of an interface circuit includes a clock generating circuit, a pulse generating circuit, an overlapped multiplexing circuit, and an output circuit. The clock generating circuit generates a plurality of clocks having different phases. The pulse generating circuit generates a plurality of pulses based on the plurality of clocks. The overlapped multiplexing circuit receives a plurality of input signals in parallel, and sequentially outputs a plurality of overlapped signals based on the plurality of clocks, the plurality of input signals, and the plurality of pulses, and each overlapped signal includes bit values of two input signals among the plurality of input signals. The output circuit serially outputs bit values of the plurality of input signals in series based on the plurality of overlapped signal.

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