US Patent Application 17988485. BOUNDARY GATE STRUCTURE FOR DIFFUSION BREAK IN 3D-STACKED SEMICONDUCTOR DEVICE simplified abstract
BOUNDARY GATE STRUCTURE FOR DIFFUSION BREAK IN 3D-STACKED SEMICONDUCTOR DEVICE
Organization Name
Inventor(s)
Saehan Park of Clifton Park NY (US)
Panjae Park of Clifton Park NY (US)
Seungyoung Lee of Clifton Park NY (US)
Byounghak Hong of Latham NY (US)
BOUNDARY GATE STRUCTURE FOR DIFFUSION BREAK IN 3D-STACKED SEMICONDUCTOR DEVICE - A simplified explanation of the abstract
- This abstract for appeared for US patent application number 17988485 Titled 'BOUNDARY GATE STRUCTURE FOR DIFFUSION BREAK IN 3D-STACKED SEMICONDUCTOR DEVICE'
Simplified Explanation
The abstract describes a three-dimensional stacked semiconductor device. It consists of a lower active region divided into two sub-regions (lower-1active and lower-2active) by a lower boundary gate structure. Above the lower active region is an upper active region divided into two sub-regions (upper-1active and upper-2active) by an upper boundary gate structure. The key feature is that either the lower or upper boundary gate structure is reverse-biased, which means it is used to electrically isolate one sub-region from the other. This allows for better control and functionality of the device.
Original Abstract Submitted
Provided is a three-dimensional stacked (3D-stacked) semiconductor device which includes: a lower active region divided into a lower-1active sub-region and a lower-2active sub-region by at least one lower boundary gate structure; and an upper active region, above the lower active region, divided into an upper-1active sub-region and an upper-2active sub-region by at least one upper boundary gate structure, wherein at least one of the lower boundary gate structure and the upper boundary gate structure is reverse-biased to electrically isolate the lower-1active sub-region from the lower-2active sub-region, and/or electrically isolate the upper-1active sub-region from the upper-2active sub-region
