US Patent Application 17964092. SEMICONDUCTOR MEMORY DEVICES AND ELECTRONIC DEVICES INCLUDING THE SEMICONDUCTOR MEMORY DEVICES simplified abstract
Contents
SEMICONDUCTOR MEMORY DEVICES AND ELECTRONIC DEVICES INCLUDING THE SEMICONDUCTOR MEMORY DEVICES
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SEMICONDUCTOR MEMORY DEVICES AND ELECTRONIC DEVICES INCLUDING THE SEMICONDUCTOR MEMORY DEVICES - A simplified explanation of the abstract
- This abstract for appeared for US patent application number 17964092 Titled 'SEMICONDUCTOR MEMORY DEVICES AND ELECTRONIC DEVICES INCLUDING THE SEMICONDUCTOR MEMORY DEVICES'
Simplified Explanation
This abstract describes a semiconductor memory device that includes various components such as a data input/output (I/O) buffer, a data first-in/first-out (FIFO) circuit, and an address comparing circuit. The data I/O buffer is responsible for providing write data to the memory cell array. The data FIFO circuit consists of multiple data FIFO buffers that store read data obtained from the memory cell array during different read operations. The data FIFO circuit then outputs the data stored in one of these buffers based on a set of sub matching signals. The address comparing circuit keeps track of previous addresses along with first commands that specify the read operations, and it generates the sub matching signals by comparing these previous addresses with the current address accompanied by a second command for the present read operation.
Original Abstract Submitted
A semiconductor memory device includes a data input/output (I/O) buffer, a data first-in/first-out (FIFO) circuit, an address comparing circuit. The data I/O buffer provides a memory cell array with write data. The data FIFO circuit includes plurality of data FIFO buffers which store read data that is read from the memory cell array in each of a plurality of read operations. The data FIFO circuit outputs data stored in one of the plurality of data FIFO buffers based on a plurality of sub matching signals. The address comparing circuit sequentially stores previous addresses accompanied by first commands designating the plurality of read operations and generates the plurality of sub matching signals based on a comparison of the previous addresses and a present address accompanied by a second command designating a present read operation.
