US Patent Application 17887203. REVERSED HIGH ASPECT RATIO CONTACT (HARC) STRUCTURE AND PROCESS simplified abstract
Contents
REVERSED HIGH ASPECT RATIO CONTACT (HARC) STRUCTURE AND PROCESS
Inventors
Buhyun Ham of Mechanicville NY (US)
Byounghak Hong of Albany NY (US)
Myunghoon Jung of Clifton Park NY (US)
Wonhyuk Hong of Clifton Park NY (US)
Seungyoung Lee of Clifton Park NY (US)
Kang-ill Seo of Albany NY (US)
REVERSED HIGH ASPECT RATIO CONTACT (HARC) STRUCTURE AND PROCESS - A simplified explanation of the abstract
- This abstract for appeared for patent application number 17887203 Titled 'REVERSED HIGH ASPECT RATIO CONTACT (HARC) STRUCTURE AND PROCESS'
Simplified Explanation
The abstract describes a semiconductor chip architecture that includes a wafer with different layers on one side. The front-end-of-line (FEOL) layer consists of a semiconductor device and an interlayer dielectric (ILD) structure. The wafer also has a shallow trench isolation (STI) structure. On top of the FEOL layer, there is a middle-of-line (MOL) layer with a contact and a via connected to the contact. An insulating layer is present on the same side of the wafer, adjacent to the via. The wafer also has a power rail that goes through it from the opposite side. The via extends vertically through the ILD structure, STI structure, and wafer to make contact with the power rail.
Original Abstract Submitted
Provided is a semiconductor chip architecture including a wafer, a front-end-of-line (FEOL) layer on a first side of the wafer, the FEOL layer including a semiconductor device and an interlayer dielectric (ILD) structure on the semiconductor device on the first side of the wafer, a shallow trench isolation (STI) structure in the wafer, and the wafer, a middle-of-line (MOL) layer provided on the first FEOL layer, the MOL layer including a contact and a via connected to the contact, an insulating layer on the first side of the wafer and adjacent to the via in a horizontal direction, a power rail penetrating the wafer from a second side of the wafer opposite to the first side, wherein the via extends through the ILD structure, the STI structure, and the wafer in a vertical direction to contact the power rail.
