US Patent Application 17882203. 3D-STACKED SEMICONDUCTOR DEVICE INCLUDING SOURCE/DRAIN INNER SPACERS FORMED USING CHANNEL ISOLATION STRUCTURE INCLUDING THIN SILICON LAYER simplified abstract
3D-STACKED SEMICONDUCTOR DEVICE INCLUDING SOURCE/DRAIN INNER SPACERS FORMED USING CHANNEL ISOLATION STRUCTURE INCLUDING THIN SILICON LAYER
Organization Name
Inventor(s)
Jaejik Baek of Watervliet NY (US)
Byounghak Hong of Albany NY (US)
Inchan Hwang of Schenectady NY (US)
Kang-ill Seo of Albany NY (US)
3D-STACKED SEMICONDUCTOR DEVICE INCLUDING SOURCE/DRAIN INNER SPACERS FORMED USING CHANNEL ISOLATION STRUCTURE INCLUDING THIN SILICON LAYER - A simplified explanation of the abstract
- This abstract for appeared for US patent application number 17882203 Titled '3D-STACKED SEMICONDUCTOR DEVICE INCLUDING SOURCE/DRAIN INNER SPACERS FORMED USING CHANNEL ISOLATION STRUCTURE INCLUDING THIN SILICON LAYER'
Simplified Explanation
The abstract describes a multi-stack semiconductor device that includes a substrate and two nanosheet transistors stacked on top of each other. The lower nanosheet transistor has a lower channel structure, a lower gate structure, and lower source/drain regions. It is isolated from the upper nanosheet transistor by at least one lower inner spacer. The upper nanosheet transistor has an upper channel structure, an upper gate structure, and upper source/drain regions. It is isolated from the lower nanosheet transistor by at least one upper inner spacer. There is also an isolation structure between the lower and upper channel structures. The abstract mentions that a spacer structure made of the same material as the inner spacers is formed at the side of the isolation structure.
Original Abstract Submitted
Provided is a multi-stack semiconductor device including: a substrate; a lower nanosheet transistor including a lower channel structure; a lower gate structure surrounding the lower channel structure and including a gate dielectric layer; lower source/drain regions at both ends of the lower channel structure; and at least one lower inner spacer isolating the lower source/drain regions from the lower gate structure; an upper nanosheet transistor, on the lower nanosheet transistor, including an upper channel structure; an upper gate structure surrounding the upper channel structure and including the gate dielectric layer; upper source/drain regions at both ends of the upper channel structure; and at least one upper inner spacer isolating the upper source/drain regions from the upper gate structure; and an isolation structure between the lower and upper channel structures, wherein a spacer structure including a same material forming the lower or upper inner spacer is formed at a side of the isolation structure.
