US Patent Application 17879140. Integrated Circuitry, Memory Arrays Comprising Strings Of Memory Cells, Methods Used In Forming Integrated Circuitry, And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells simplified abstract
Contents
- 1 Integrated Circuitry, Memory Arrays Comprising Strings Of Memory Cells, Methods Used In Forming Integrated Circuitry, And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 Integrated Circuitry, Memory Arrays Comprising Strings Of Memory Cells, Methods Used In Forming Integrated Circuitry, And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Original Abstract Submitted
Integrated Circuitry, Memory Arrays Comprising Strings Of Memory Cells, Methods Used In Forming Integrated Circuitry, And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
Organization Name
Inventor(s)
David H. Wells of Boise ID (US)
Pengyuan Zheng of Boise ID (US)
Amritesh Rai of Tigard OR (US)
Integrated Circuitry, Memory Arrays Comprising Strings Of Memory Cells, Methods Used In Forming Integrated Circuitry, And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells - A simplified explanation of the abstract
This abstract first appeared for US patent application 17879140 titled 'Integrated Circuitry, Memory Arrays Comprising Strings Of Memory Cells, Methods Used In Forming Integrated Circuitry, And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
Simplified Explanation
The patent application describes a method for forming a memory array using a stack of insulative and conductive tiers.
- The memory array includes channel-material strings of memory-cell strings that extend through the insulative and conductive tiers.
- Conductive vias are formed above the channel-material strings and are directly electrically coupled to them.
- Digitlines are formed above the conductive vias and are also directly electrically coupled to them.
- The digitlines are formed by depositing lower elemental-form tungsten directly on top of the conductive vias.
- The lower elemental-form tungsten is exposed to oxygen-containing gas or plasma to form WO (tungsten oxide) with a thickness of 0-30 Angstroms.
- Upper elemental-form tungsten is then physically vapor deposited directly on top of the WO.
- The patent application also mentions other embodiments and structures.
Original Abstract Submitted
A method used in forming a memory array comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory-cell strings extend through the insulative and conductive tiers. Conductive vias are formed above and individually directly electrically coupled to individual of the channel-material strings. Digitlines are formed above and are individually directly electrically coupled to a plurality of individual of the conductive vias there-below. The forming of the digitlines comprises forming lower elemental-form tungsten directly against tops of the individual conductive vias. The lower elemental-form tungsten is exposed to oxygen-containing gas or plasma to form WO, where “x” is greater than 0 and no more than 3.0. The WOhas a maximum thickness greater than 0 and no more than 30 Angstroms in a finished construction. Upper elemental-form tungsten is physical vapor deposited directly against the WO. Other embodiments, including structure, are disclosed.
