US Patent Application 17838446. SYSTEMS AND METHODS FOR FLUSH PLUS RELOAD CACHE SIDE-CHANNEL ATTACK MITIGATION simplified abstract
Contents
SYSTEMS AND METHODS FOR FLUSH PLUS RELOAD CACHE SIDE-CHANNEL ATTACK MITIGATION
Organization Name
Microsoft Technology Licensing, LLC==Inventor(s)==
[[Category:Ishwar Agarwal of Redmond WA (US)]]
[[Category:Bharat Pillilli of El Dorado Hills CA (US)]]
[[Category:Vishal Soni of Redmond WA (US)]]
SYSTEMS AND METHODS FOR FLUSH PLUS RELOAD CACHE SIDE-CHANNEL ATTACK MITIGATION - A simplified explanation of the abstract
This abstract first appeared for US patent application 17838446 titled 'SYSTEMS AND METHODS FOR FLUSH PLUS RELOAD CACHE SIDE-CHANNEL ATTACK MITIGATION
Simplified Explanation
- The patent application describes a method for mitigating a side-channel timing attack in a system with a processor and cache. - The method involves receiving a first instruction that is designed to flush at least one cache line from the processor's cache. - Prior to executing the first instruction, the method automatically maps it to a second instruction that prevents the cache line from being flushed, even if the first instruction is received. - This technique helps protect against cache side-channel attacks by preventing the attacker from exploiting timing information obtained from cache flush operations. - The innovation aims to enhance the security of systems with processors and caches by reducing the vulnerability to side-channel attacks.
Original Abstract Submitted
Systems and methods related to flush plus reload cache side-channel attack mitigation are described. An example method for mitigating a side-channel timing attack in a system including a processor having at least one cache is described. The method includes receiving a first instruction, where the first instruction, when executed by the processor, is configured to flush at least one cache line from the at least one cache associated with the processor. The method further includes, prior to execution of the first instruction by the processor, automatically mapping the first instruction to a second instruction such that the at least one cache line is not flushed from the at least one cache even in response to receiving the first instruction.
