US Patent Application 17828708. SYSTEMS AND METHODS OF REDUCING DETECTION ERROR AND DUTY ERROR IN MEMORY DEVICES simplified abstract

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SYSTEMS AND METHODS OF REDUCING DETECTION ERROR AND DUTY ERROR IN MEMORY DEVICES

Organization Name

SanDisk Technologies LLC

Inventor(s)

Jang Woo Lee of San Ramon CA (US)

Srinivas Rajendra of San Jose CA (US)

Anil Pai of San Jose CA (US)

Venkatesh Prasad Ramachandra of San Jose CA (US)

SYSTEMS AND METHODS OF REDUCING DETECTION ERROR AND DUTY ERROR IN MEMORY DEVICES - A simplified explanation of the abstract

This abstract first appeared for US patent application 17828708 titled 'SYSTEMS AND METHODS OF REDUCING DETECTION ERROR AND DUTY ERROR IN MEMORY DEVICES

Simplified Explanation

The patent application describes systems and methods for reducing detection and duty cycle errors in memory devices.

  • The invention combines a write duty cycle adjuster with write training techniques.
  • The write duty cycle adjuster adjusts the duty cycle of a clock signal that coordinates a data signal with a data operation on the memory device.
  • This adjustment is based on an error in the duty cycle, helping to reduce errors in the memory device.
  • The write training operations detect any skew between the data signal and the clock signal.
  • If a skew is detected, the sampling transition of the duty cycle of the clock signal is adjusted to align with a valid data window of the data signal.
  • This alignment helps to ensure accurate data transfer and reduce errors in the memory device.


Original Abstract Submitted

Systems and methods are provided that combine a write duty cycle adjuster with write training to reduce detection and duty cycle errors in memory devices. Various embodiments herein perform write duty cycle adjuster operations to adjust a duty cycle of a clock signal that coordinates a data signal with a data operation on the memory device based on an error in the duty cycle, and performs write training operations to detect a skew between the data signal and the clock signal and adjust a sampling transition of the duty cycle of the clock signal to align with a valid data window of the data signal.