US Patent Application 17825741. SEMICONDUCTOR DEVICE INCLUDING INTERCONNECTS WITH LOWER CONTACT RESISTANCE simplified abstract

SEMICONDUCTOR DEVICE INCLUDING INTERCONNECTS WITH LOWER CONTACT RESISTANCE

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.==Inventor(s)==

[[Category:Hsi-Wen Tien of Hsinchu (TW)]]

[[Category:Hwei-Jay Chu of Hsinchu (TW)]]

[[Category:Chia-Tien Wu of Hsinchu (TW)]]

[[Category:Yung-Hsu Wu of Hsinchu (TW)]]

[[Category:Wei-Hao Liao of Hsinchu (TW)]]

[[Category:Yu-Teng Dai of Hsinchu (TW)]]

[[Category:Hsin-Chieh Yao of Hsinchu (TW)]]

[[Category:Hsin-Ping Chen of Hsinchu (TW)]]

[[Category:Chih-Wei Lu of Hsinchu (TW)]]

SEMICONDUCTOR DEVICE INCLUDING INTERCONNECTS WITH LOWER CONTACT RESISTANCE - A simplified explanation of the abstract

This abstract first appeared for US patent application 17825741 titled 'SEMICONDUCTOR DEVICE INCLUDING INTERCONNECTS WITH LOWER CONTACT RESISTANCE

Simplified Explanation

The patent application describes a semiconductor device with specific features related to its interconnect layer and dielectric layer.

• The device includes a substrate, which serves as a base for the other layers.
• An interconnect layer is placed over the substrate and contains a metal line, which is used for electrical connections.
• A dielectric layer is then placed on top of the interconnect layer and includes a via contact, which is another type of electrical connection.
• The via contact is connected to the metal line and has different dimensions in different directions.
• Specifically, the via contact is longer in one direction (first dimension) and shorter in another direction (second dimension).
• These dimensions are perpendicular to each other and also perpendicular to the length of the via contact.

Overall, the patent application focuses on a specific design for the via contact in a semiconductor device, where its dimensions are not equal and are oriented in a specific manner.

Original Abstract Submitted

A semiconductor device includes a substrate, an interconnect layer disposed over the substrate and including a metal line, and a dielectric layer disposed on the interconnect layer and including a via contact. The via contact is electrically connected to the metal line and has a first dimension in a first direction greater than a second dimension in a second direction. The first direction and the second direction are perpendicular to each other, and are both perpendicular to a longitudinal direction of the via contact.