US Patent Application 17825345. INTERCONNECT STRUCTURE INCLUDING CHARGED DIELECTRIC LAYERS simplified abstract

INTERCONNECT STRUCTURE INCLUDING CHARGED DIELECTRIC LAYERS

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.==Inventor(s)==

[[Category:Chien Hung Liu of Hsinchu County (TW)]]

[[Category:Kuo-Ching Huang of Hsinchu City (TW)]]

[[Category:Harry-Hak-Lay Chuang of Zhubei City (TW)]]

[[Category:Wei-Cheng Wu of Zhubei City (TW)]]

INTERCONNECT STRUCTURE INCLUDING CHARGED DIELECTRIC LAYERS - A simplified explanation of the abstract

This abstract first appeared for US patent application 17825345 titled 'INTERCONNECT STRUCTURE INCLUDING CHARGED DIELECTRIC LAYERS

Simplified Explanation

The patent application describes an integrated chip with multiple layers and interconnects.

• The chip includes a first dielectric layer and a conductive interconnect within it.
• A bonding layer is present above the first dielectric layer, consisting of a bonding dielectric layer and a bonding interconnect.
• A first charged dielectric layer is located at the bottom of the first dielectric layer.
• A second charged dielectric layer is located at the top of the first dielectric layer.
• The first and second charged dielectric layers have the same polarity.

Original Abstract Submitted

The present disclosure relates to an integrated chip including a first dielectric layer overlying a substrate and a first conductive interconnect within the first dielectric layer. A bonding layer is over the first dielectric layer. The bonding layer includes a bonding dielectric layer and a bonding interconnect in the bonding dielectric layer. A first charged dielectric layer is along a bottom of the first dielectric layer. A second charged dielectric layer is along a top of the first dielectric layer. The first charged dielectric layer and the second charged dielectric layer have a same polarity.