US Patent Application 17824350. METHOD TO OPTIMIZE FIRST READ VERSUS SECOND READ MARGIN BY SWITCHING BOOST TIMING simplified abstract
METHOD TO OPTIMIZE FIRST READ VERSUS SECOND READ MARGIN BY SWITCHING BOOST TIMING
Organization Name
Inventor(s)
Jia Li of San Francisco CA (US)
Behrang Bagheri of San Jose CA (US)
Keyur Payak of Santa Clara CA (US)
Long Pham of San Ramon CA (US)
METHOD TO OPTIMIZE FIRST READ VERSUS SECOND READ MARGIN BY SWITCHING BOOST TIMING - A simplified explanation of the abstract
This abstract first appeared for US patent application 17824350 titled 'METHOD TO OPTIMIZE FIRST READ VERSUS SECOND READ MARGIN BY SWITCHING BOOST TIMING
Simplified Explanation
The patent application describes an apparatus with multiple memory cells and a control circuit.
- The control circuit is responsible for performing a read operation on the memory cells.
- During the read operation, the control circuit determines the read condition of a memory cell.
- The read condition can be one of several possible conditions.
- The control circuit also determines the boost timing for the memory cell based on its read condition.
- The boost timing is a specific timing that corresponds to the read condition of the memory cell.
Original Abstract Submitted
An apparatus that comprises a plurality of memory cells and a control circuit coupled to the plurality of memory cells is disclosed. The control circuit is configured to perform a read operation. The read operation includes determining a read condition of a memory cell, where the read condition is of a plurality of read conditions and determining a boost timing for the memory cell, where the boost timing corresponds to the read condition.
