US Patent Application 17752704. SOURCE/DRAIN ISOLATION STRUCTURE, LAYOUT, AND METHOD simplified abstract

SOURCE/DRAIN ISOLATION STRUCTURE, LAYOUT, AND METHOD

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.==Inventor(s)==

[[Category:Chi-Yu Lu of Hsinchu (TW)]]

[[Category:Yi-Hsun Chiu of Hsinchu (TW)]]

[[Category:Chih-Liang Chen of Hsinchu (TW)]]

[[Category:Chih-Yu Lai of Hsinchu (TW)]]

[[Category:Shang-Hsuan Chiu of Hsinchu (TW)]]

SOURCE/DRAIN ISOLATION STRUCTURE, LAYOUT, AND METHOD - A simplified explanation of the abstract

This abstract first appeared for US patent application 17752704 titled 'SOURCE/DRAIN ISOLATION STRUCTURE, LAYOUT, AND METHOD

Simplified Explanation

The abstract describes an integrated circuit structure with specific components and their arrangement.

• The structure includes two active areas and two gate structures in a semiconductor substrate.
• The gate structures are perpendicular to the active areas and cover them.
• There is a metal-like defined (MD) segment between the gate structures, also covering the active areas.
• An isolation structure is positioned between the MD segment and one of the active areas.
• The MD segment is electrically connected to one active area and isolated from a portion of the other active area between the gate structures.

Original Abstract Submitted

An integrated circuit (IC) structure includes first and second active areas extending in a first direction in a semiconductor substrate, first and second gate structures extending in a second direction perpendicular to the first direction, wherein each of the first and second gate structures overlies each of the first and second active areas, a first metal-like defined (MD) segment extending in the second direction between the first and second gate structures and overlying each of the first and second active areas, and an isolation structure positioned between the first MD segment and the first active area. The first MD segment is electrically connected to the second active area and electrically isolated from a portion of the first active area between the first and second gate structures.